1. Field of the Invention
The present invention relates generally to an address generator for providing addresses to a linear block encoder and decoder in a data transmission system. More particularly, the present invention relates to an address generator for providing addresses to a low density parity-check code (LDPC) encoder for a write channel and decoder for a read channel in a disk drive system.
2. Description of the Related Art
FIG. 1 illustrates a conventional digital data transmission system. As shown therein, a digital data transmission system comprises a transmitting section 300 for transmitting user data to receiver 500 via communication channel 401.
The operation of transmission section 300 will now be explained. Prior to processing by transmitting section 300, input or user data maybe encoded with an error correcting code, such as the Reed/Solomon code, or run length limited encoded (RLL) or a combination thereof by encoder 302. The encoded output encoder 302 is then interleaved by deinterleaver 308 for input to linear block code encoder 304 which generates parity data in a known manner utilizing linear block codes. One example of a linear block code is a low-density parity-check code (LDPC) which is discussed by Robert G. Gallager in Low-Density Parity-Check Codes, 1963, M.I.T. Press and by Zining Wu in Coding and Iterative Detection For Magnetic Recording Channels, 2000, Kluwer Academic Publishers, the contents of each of which are incorporated in their entirety by reference. Deinterleaver 308 permutes the data so that the same data is reordered before encoding by linear block code encoder 304. By permuting or redistributing the data, deinterleaver 308 attempts to reduce the number of nearest neighbors of small distance error events. User data at the output of encoder 302 is referred to as being in the channel domain; that is the order in which data is transmitted through the channel. The order of data processed by deinterleaver 308 is referred to as being in the linear block code domain. The parity data from linear block code encoder 304 is combined with the data encoded by encoder 302 by multiplexer 306 for input to channel transmitter 310.
Transmitter 310 transmits the combined user and parity data from multiplexer 306 typically as an analog signal over communication channel 401 in the channel domain. Communication channel 401 may include any wireless, wire, optical and the like communication medium. Receiver 500 comprises a front-end circuit 502 comprising analog to digital and equalization circuits. The digital signal front-end circuit 502 is input to soft channel decoder 504, which provides probability information of the detected data. Soft channel decoder 504 may be implemented by a Soft Viterbi Detector or the like. The output of the soft channel decoder 504, which is in the channel domain, is converted into the linear block code domain by deinterleaver 510. Deinterleaver 510 is constructed similarly to deinterleaver 308. Soft linear block code decoder 506 utilizes this information and the parity bits to decode the received data. One output of soft linear block code decoder 506 is fed back to soft channel decoder 504 via interleaver 512, which converts data in the linear block code domain to the channel domain. Interleaver 512 is constructed to perform the reverse operations of deinterleaver 510. Soft channel decoder 504 and soft linear block code decoder 506 operate in an iterative manner to decode the detected data.
The other output of soft linear block code decoder 506 is converted from the linear block domain to the channel domain by interleaver 514. Interleaver 514 is constructed similarly to interleaver 512. The output of interleaver 514 is passed on for further processing to decoder 508. Decoder 508 is implemented to perform the reverse operations of encoder 302.
FIG. 9 is an example of deinterleaver 308 (510) and an example of interleaver 514 (512). As shown therein, a codeword comprising bits b1, b2, b3, b4, b5 and b6 are input in time order of the first bit b1 to the last bit b6 to deinterleaver 308 (510). Deinterleaver 308 reorders the bit in accordance with the table below and outputs bit b3 first to the last bit b5 as the reordered codeword.
Input bit orderOutput bit order132234465165
Interleaver 514 (512) performs the inverse operation of deinterleaver 308 (510). Interleaver 514 (512) takes, for example, the reordered codeword, bit b3 being first and bit b5 being last, and outputs a codeword in the original order, bit b1 being first and bit b6 being last, as shown in the table below.
Input bit orderOutput bit order312243641556
The implementation of conventional interleaver described above is complicated and these circuits are difficult to design, especially when processing data blocks of the size of thousands of bits. Moreover, an interleaver (or deinterleaver) for processing 5000 bits requires a large look-up table (LUT) for performing the interleaving (deinterleaving) operations. Such conventional implementation requires approximately thousands of cycles, which is inconsistent with the requirements of ever increasing high data transfer rates. The linear block code encoder must have access to all bits in the same equation at one time. Memory structures such as SRAM are not efficient for access data required by the linear block encoder, and more expensive memory structures (in terms of fabrication cost, size and power consumption), such as registers and flip flops may be employed. As can be seen from FIG. 1, the conventional system requires additional circuitry for the two deinterleavers.
Another example of an interleaver is shown in FIG. 10.
The interleaver shown in FIG. 10 comprises a swap circuit 810 for swapping bits in accordance with a predefined table to assure that parity bits are not placed in inappropriate positions. The data is then shifted by shifting circuit 820, so that each of the code words is interleaved in a different manner. The output of which is then interleaved by inner interleave circuit 830, in which the size of the codewords corresponds to the size of the LDPC codewords. As such the interleaver is highly coupled to the parity-check matrix. As used herein the deinterleaver performs the inverse function as the interleaver. As will be appreciated by one of ordinary skill in the art, the term deinterleaver may be used for the term interleaver, so long as the term interleavcr is used for the term deinterleaver.